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Tom's Hardware tests AMD Zen 6 EPYC Venice on TSMC N2P
Jake Roach of Tom's Hardware said AMD's Zen 6 EPYC Venice chips use TSMC's N2P node and that a dual EPYC 9996 with 1,024 threads was 93% ahead of a dual Zen 5 9965 in SPEC CPU 2026 integer throughput.
- Our desk updated its story
Tom's Hardware published an architecture and benchmark look at AMD's Zen 6 EPYC Venice server processors on Nov. 10, written by Jake Roach, who said the chips are the first to debut the Zen 6 design1.
The outlet said Zen 6 is built on TSMC's N2P manufacturing node and expands the Zen 5 core, which it described as a ground-up redesign1.
Roach wrote that a redesigned vector engine adds native half-precision FP16 support alongside 32-bit precision, and that integer schedulers are split so more instructions can be in flight1.
Across the package, Tom's Hardware said AMD replaced the prior single I/O die with two I/O dies, giving the SP7 platform 16 memory channels, at the cost of PCIe 6.0 lanes versus the previous generation and the SP8 platform1.
The review said a standard Zen 6 core complex die now scales to 12 cores, while a Zen 6c die packs 32 cores, up from eight and 16 cores on Zen 5 and Zen 5c; it also said Zen 6c doubled shared L3 per core, which it described as effectively quadrupling L3 versus Zen 5c because the die has twice as many cores1.
In Tom's Hardware's tests, a dual-socket 256-core EPYC 9996 configuration with 1,024 threads came out 93% ahead of a 768-thread dual EPYC 9965 server in SPEC CPU 2026's integer throughput test, the review said1.
The publication's headline also compared the frequency-oriented EPYC 9686F with Nvidia's Vera CPU; suite-by-suite scores beyond the SPEC integer result were not fully readable without a membership wall and are not restated here1.
Tom's Hardware said it had been testing two Venice chips for several weeks and framed the work as a look at how Zen 6 departs from Zen 5 ahead of an expected consumer Olympic Ridge launch next year1.